数字集成电路:设计透视第2版

数字集成电路
9.2
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作者: [德] (Rabaey J.M.)
出版社: 清华大学出版社
2004-03
版次: 1
ISBN: 9787302079682
定价: 68.00
装帧: 平装
开本: 16开
纸张: 胶版纸
页数: 761页
正文语种: 简体中文,英语
  •   (1)将数字集成电路设计中电路与系统的视角统一起来,在系统深入地介绍了深亚微米条件下半导体器件的知识和最基本的反相器后,作者逐渐将这些基础知识引入到更加复杂的模块,比如门、寄存器、控制器、加法器、乘法器和存储器等。在深亚微米的设计条件下,设计者不仅仅需要考虑整个系统的设计问题,还要随时警惕在电路级——比如器件和连线所带来的问题。(2)本书是第一本将数字集成电路设计问题集中在深亚微米条件下的参考书,并且提供了一个深亚微米条件下的简晶体管模型。另外针对深亚微米条件下设计人员所面对的新挑战,例如互连线问题、信号完整性问题、时钟分布问题、功耗问题等,全书都做了非常详细的论述。(3)书中的内容紧扣当今数字集成电路设计的核心问题,并通过大量的设计实例向读者介绍了最新的设计技术和工程发展现状与趋势。 Chapterl:Introduction
    1.1AHistoricalPerspective
    1.2IssuesinDigitalIntegratedCircuitDesign
    1.3ToProbeFurther
    1.4Exercises
    PART1:ACIRCUITPERSPECTIVE
    Chapter2:TheDevices
    2.1Introduction
    2.2TheDiode
    2.2.1AFirstGlanceattheDevice
    2.2.2StaticBehavior
    2.2.3Dynamic,orTransient,Behavior
    2.2.4TheActualDiode-SecondaryEffects
    2.2.5TheSPICEDiodeModel
    2.3TheMOS(FET)Transistor
    2.3.1AFirstGlanceattheDevice
    2.3.2StaticBehavior
    2.3.3DynamicBehavior
    2.3.4TheActualMOSTransistor-SecondaryEffects
    2.3.5SPICEModelsfortheMOSTransistor
    2.4TheBipolarTransistor
    2.4.1AFirstGlanceattheDevice
    2.4.2StalicBehavior
    2.4.3DynamicBehavior
    2.4.4TheActualBipolarTransistor-SecondaryEffects
    2.4.5SPICEModelsfortheBipolarTransistor
    2.5AWordonProcessVariations
    2.6Perspective:FutureDeviceDevelopments
    2.7Summary
    2.8ToProbeFurther
    2.9ExercisesandDesignProblems
    AppendlxA:LayoutDesignRules
    AppendlxB:Small-SlgnalModels
    Chapter3:TheInverter
    3.1Introduction
    3.2DelinitionsandProperties
    3.2.1AreaandComplexity
    3.2.2FunctionalityandRobustness:TheStaticBehavior
    3.2.3Performance:TheDynamicBehavior
    3.2.4PowerandEnergyConsumption
    3.3TheStaticCMOSInvener
    3.3.1AFirstGlance
    3.3.2EvaluatingtheRobustnessoftheCMOSInverter:TheStaticBehavior
    3.3.3PerfonnanceofCMOSInverter:TheDynamicBehavior
    3.3.4PowerConsumptionandPower-DelayProduct
    3.3.5ALookintotheFuture:EffectsofTechnologyScaling
    3.4TheBipolarECLInverter
    3.4.1IssuesinBipolarDigitalDesign:ACaseStudy
    3.4.2TheEmitter-CoupledLogic(ECL)GateataGlance
    3.4.3RobustnessandNoiseImmunity:TheSteady-StateCharacteristics
    3.4.4ECLSwitchingSpeed:ThcTransientBehavior
    3.4.5PowerConsumption
    3.4.6LookingAhead:ScalingtheTechnology
    3.5Perspective:Area,Perfonnance,andDissipation
    3.6Summary
    3.7ToProbeFurther
    3.8ExercisesandDesignProblems
    Chapter4:DesigningCombinationalLogkCatesinCMOS
    4.1Introduction
    4.2StaticCMOSDesign
    4.2.1ComplementaryCMOS
    4.2.2RatioedLogic
    4.2.3Pass-TransistorLogic
    4.3DynamicCMOSDesign
    4.3.1DynamicLogic:BasicPrinciples
    4.3.2PerfonnanceofDynamicLogic
    4.3.3NoiseConsiderationsinDynamicDesign
    4.3.4CascadingDynamicGates
    4.4PowerConsumptioninCMOSGates
    4.4.1SwitchingActivityofaLogicGate
    4.4.2GlitchinginStaticCMOSCircuits
    4.4.3Short-CircuitCurrentsinStaticCMOSCircuits
    4.4.4AnalyzingPowerConsumptionUsingSPICE
    4.4.5Low-PowerCMOSDesign
    4.5Perspective:HowtoChooseaLogicStyle
    4.6Summary
    4.7ToProbeFurther
    4.8ExercisesandDesignProblems
    AppendixC:LayoutTechniquesforComplexCates
    Chapter5:VeryHighPerfonnanceDigitalCircuits
    5.1Introduction
    5.2BipolarGateDesign
    5.2.1LogicDesigninECL
    5.2.2DifferentialECL
    5.2.3CurrentModeLogic
    5:2.4ECLwithActivePull-Downs
    5.2.5AltemativeBipolarLogicStyles
    5.3TheBiCMOSApproach
    5.3.1TheBiCMOSGateataGlance
    5.3.2TheStaticBehaviorandRobustnessIssues
    5.3.3PerfonnanceoftheBiCMOSInverter
    5.3.4PowerConsumption
    5.3.5TechnologyScaling
    5.3.6DesigningBiCMOSDigitalGates
    5.4DigitalGalliumArsenideDesign*
    5.4.1GaAsDevicesandTheirProperties
    5.4.2GaAsDigitalCircuitDesign
    5.5Low-TemperatureDigitalCircuits*
    5.5.1Low-TemperatureSiliconDigitalCircuits
    5.5.2SuperconductingLogicCircuits
    5.6Perspective:WhentoUseHigh-PerformanceTechnologies
    5.7Summary
    5.8ToProbeFurther
    5.9ExercisesandDesignProblems
    AppendlxD:TheSchottky-BamerOiode
    Chapter6:DesigningSequentialLogicCircuits
    6.1Introduction
    6.2StaticSequentialCircuits
    6.2.1Bistability
    6.2.2Flip-FlopClassification
    6.2.3Master-SlaveandEdge-TriggeredFFs
    6.2.4CMOSStaticFlip-Flops
    6.2.5BipolarStaticFlip-Flops
    6.3DynamicSequentia)Circuits
    6.3.1ThePseudostaticLatch
    6.3.2TheDynamicTwo-PhaseFlip-Flop
    6.3.3TheC2MOSLatch
    6.3.4NORA-CMOS-ALogicStyleforPipelinedStructures
    6.3.5TrueSingle-PhaseClockedLogic(TSPCL)
    6.4Non-BistableSequentialCircuits
    6.4.1TheSchmittTrigger
    6.4.2MonostableSequentialCircuits
    6.4.3AstableCircuits
    6.5Perspective:ChoosingaClockingStrategy
    6.6Summary
    6.7ToProbeFunher
    6.8ExercisesandDesignProblems
    PART11:ASYSTEMSPERSPECTIVE
    Chapter7:DesigningArithmeticBuildingBlocks
    7.1Introduction
    7.2DatapathsinDigitalProcessorArchitectures
    7.3TheAdder
    7.3.1TheBinaryAdder:Definitions
    7.3.2TheFullAdder:CircuitDesignConsiderations
    7.3.3TheBinaryAdder:LogicDesignConsiderations
    7.4TheMultiplier
    7.4.1TheMultiplier:Definitions
    7.4.2TheArrayMultiplier
    7.4.3OtherMultiplierStructures
    7.5TheShifter
    7.5.1BarrelShifter
    7.5.2LogarithmicShifter
    7.6OtherArithmeticOperators
    7.7PowerConsiderationsinDatapathStructures
    7.7.1ReducingtheSupplyVoltage
    7.7.2ReducingtheEffectiveCapacitance
    7.8Perspective:De.signasaTrade-off
    7.9Summary
    7.10ToProbeFurther
    7.11ExercisesandDesignProblems
    AppendixE:FromDatapathSchematicstoLayout
    Chapter8:CopingwlthInterconnect
    8.1Introduction
    8.2CapacitiveParasitics
    8.2.1ModelingInterconnectCapacitance
    8.2.2CapacitanceandReliability-CrossTalk
    8.2.3CapacitanceandPerformanceinCMOS
    8.2.4CapacitanceandPerformanceinBipolarDesign
    8.3ResistiveParasitics
    8.3.1ModelingandScalingofInterconnectResistance
    8.3.2ResistanceandReliability-OhmicVoltageDrop
    8.3.3Electromigration
    8.3.4ResistanceandPerformance-RCDelay
    8.4InductiveParasitics
    8.4.1SourcesofParasiticInductances
    8.4.2InductanceandReliability-VoltageDrop
    8.4.3InductanceandPerformance-TransmissionLin5eEffects
    8.5CommentsonPackagingTechnology
    8.5.1PackageMaterials
    8.5.2InterconnectLevels
    8.5.3ThennalConsiderationsinPackaging
    8.6Perspective:WhentoConsiderInterconnectParasitics
    8.7ChapterSummary
    8.8ToProbeFurther
    8.9ExercisesandDesignProblems
    Chapter9:TimingIssuesinDigitalCircuits
    9.1Introduction
    9.2ClockSkewandSequentialCircuitPerformance
    9.2.1Single-PhaseEdge-TriggeredClocking
    9.2.2Two-PhaseMaster-SlaveClocking
    9.2.3OtherClockingStyles
    9.2.4HowtoCounterClockSkewProblems
    9.2.5CaseStudy-TheDigitalAlpha21164Microprocessor
    9.3Self-TimedCircuitDesign*
    9.3.1Selt-TimedConcept
    9.3.2Completion-SignalGeneration
    9.3.3Self-TimedSignaling
    9.4SynchronizersandArbiters*
    9.4.1Synchronizers-ConceptandImplementation
    9.4.2Arbiters
    9.5ClockGenerationandSynchronization*
    9.5.1ClockGenerators
    9.5.2SynchronizationattheSystemLevel
    9.6Perspective:SynchronousversusAsynchronousDesign
    9.7Summary
    9.8ToProbeFurther
    9.9Exerci.sesandDesignProblems
    Chapter10:DesigningMemoryandArrayStructures
    10.1Introduction
    10.2SemiconductorMemories--AnIntroduction
    10.2.1MemoryClassification
    10.2.2MemoryArchitecturesandBuildingBlocks
    10.3TheMemoryCore
    10.3.1Read-OnlyMemories
    10.3.2NonvolatileRead-WriteMemories
    10.3.3Read-WriteMemories(RAM)
    10.4MemoryPeripheralCircuitry
    10.4.1TheAddressDecoders
    10.4.2SenseAmplifiers
    10.4.3Drivers/Buffers
    10.4.4TimingandControl
    10.5MemoryReliabilityandYield
    10.5.1Signal-To-NoiseRatio
    10.5.2Memoryyield
    10.6CaseStudiesinMemoryDesign
    10.6.1TheProgrammableLogicArray(PLA)
    10.6.2A4MbitSRAM
    10.7Perspective:SemiconductorMemoryTrendsandEvolutions
    10.8Summary
    10.9ToProbeFurther
    10.10ExercisesandDesignProblems
    Chapterll:DeslgnMethodologles
    11.1Introduction
    11.2DesignAnalysisandSimulation
    11.2.1RepresentingDigitalDataasaContinuousEntity
    11.2.2RepresentingDataasaDiscreteEntity
    11.2.3UsingHigher-LevelDataModels
    11.3DesignVerification
    11.3.1ElectricalVerification
    11.3.2TimingVerification
    11.3.3Functional(orFonnal)Verification
    11.4ImplementationApproaches
    11.4.1CustomCircuitDesign
    11.4.2Cell-BasedDesignMethodology
    11.4.3Anay-BasedImplementationApproaches
    11.5DesignSynthesis
    11.5.1CircuitSynthesis
    11.5.2LogicSynthesis
    11.5.3ArchitectureSynthesis
    11.6ValidationandTestingofManufacturedCircuits
    11.6.1TestProcedure
    11.6.2DesignforTestability
    11.6.3Test-PattemGeneration
    11.7PerspectiveandSummary
    11.8ToProbeFurther
    11.9ExercisesandDesignProblems
    ProblemSolutions
  • 内容简介:
      (1)将数字集成电路设计中电路与系统的视角统一起来,在系统深入地介绍了深亚微米条件下半导体器件的知识和最基本的反相器后,作者逐渐将这些基础知识引入到更加复杂的模块,比如门、寄存器、控制器、加法器、乘法器和存储器等。在深亚微米的设计条件下,设计者不仅仅需要考虑整个系统的设计问题,还要随时警惕在电路级——比如器件和连线所带来的问题。(2)本书是第一本将数字集成电路设计问题集中在深亚微米条件下的参考书,并且提供了一个深亚微米条件下的简晶体管模型。另外针对深亚微米条件下设计人员所面对的新挑战,例如互连线问题、信号完整性问题、时钟分布问题、功耗问题等,全书都做了非常详细的论述。(3)书中的内容紧扣当今数字集成电路设计的核心问题,并通过大量的设计实例向读者介绍了最新的设计技术和工程发展现状与趋势。
  • 目录:
    Chapterl:Introduction
    1.1AHistoricalPerspective
    1.2IssuesinDigitalIntegratedCircuitDesign
    1.3ToProbeFurther
    1.4Exercises
    PART1:ACIRCUITPERSPECTIVE
    Chapter2:TheDevices
    2.1Introduction
    2.2TheDiode
    2.2.1AFirstGlanceattheDevice
    2.2.2StaticBehavior
    2.2.3Dynamic,orTransient,Behavior
    2.2.4TheActualDiode-SecondaryEffects
    2.2.5TheSPICEDiodeModel
    2.3TheMOS(FET)Transistor
    2.3.1AFirstGlanceattheDevice
    2.3.2StaticBehavior
    2.3.3DynamicBehavior
    2.3.4TheActualMOSTransistor-SecondaryEffects
    2.3.5SPICEModelsfortheMOSTransistor
    2.4TheBipolarTransistor
    2.4.1AFirstGlanceattheDevice
    2.4.2StalicBehavior
    2.4.3DynamicBehavior
    2.4.4TheActualBipolarTransistor-SecondaryEffects
    2.4.5SPICEModelsfortheBipolarTransistor
    2.5AWordonProcessVariations
    2.6Perspective:FutureDeviceDevelopments
    2.7Summary
    2.8ToProbeFurther
    2.9ExercisesandDesignProblems
    AppendlxA:LayoutDesignRules
    AppendlxB:Small-SlgnalModels
    Chapter3:TheInverter
    3.1Introduction
    3.2DelinitionsandProperties
    3.2.1AreaandComplexity
    3.2.2FunctionalityandRobustness:TheStaticBehavior
    3.2.3Performance:TheDynamicBehavior
    3.2.4PowerandEnergyConsumption
    3.3TheStaticCMOSInvener
    3.3.1AFirstGlance
    3.3.2EvaluatingtheRobustnessoftheCMOSInverter:TheStaticBehavior
    3.3.3PerfonnanceofCMOSInverter:TheDynamicBehavior
    3.3.4PowerConsumptionandPower-DelayProduct
    3.3.5ALookintotheFuture:EffectsofTechnologyScaling
    3.4TheBipolarECLInverter
    3.4.1IssuesinBipolarDigitalDesign:ACaseStudy
    3.4.2TheEmitter-CoupledLogic(ECL)GateataGlance
    3.4.3RobustnessandNoiseImmunity:TheSteady-StateCharacteristics
    3.4.4ECLSwitchingSpeed:ThcTransientBehavior
    3.4.5PowerConsumption
    3.4.6LookingAhead:ScalingtheTechnology
    3.5Perspective:Area,Perfonnance,andDissipation
    3.6Summary
    3.7ToProbeFurther
    3.8ExercisesandDesignProblems
    Chapter4:DesigningCombinationalLogkCatesinCMOS
    4.1Introduction
    4.2StaticCMOSDesign
    4.2.1ComplementaryCMOS
    4.2.2RatioedLogic
    4.2.3Pass-TransistorLogic
    4.3DynamicCMOSDesign
    4.3.1DynamicLogic:BasicPrinciples
    4.3.2PerfonnanceofDynamicLogic
    4.3.3NoiseConsiderationsinDynamicDesign
    4.3.4CascadingDynamicGates
    4.4PowerConsumptioninCMOSGates
    4.4.1SwitchingActivityofaLogicGate
    4.4.2GlitchinginStaticCMOSCircuits
    4.4.3Short-CircuitCurrentsinStaticCMOSCircuits
    4.4.4AnalyzingPowerConsumptionUsingSPICE
    4.4.5Low-PowerCMOSDesign
    4.5Perspective:HowtoChooseaLogicStyle
    4.6Summary
    4.7ToProbeFurther
    4.8ExercisesandDesignProblems
    AppendixC:LayoutTechniquesforComplexCates
    Chapter5:VeryHighPerfonnanceDigitalCircuits
    5.1Introduction
    5.2BipolarGateDesign
    5.2.1LogicDesigninECL
    5.2.2DifferentialECL
    5.2.3CurrentModeLogic
    5:2.4ECLwithActivePull-Downs
    5.2.5AltemativeBipolarLogicStyles
    5.3TheBiCMOSApproach
    5.3.1TheBiCMOSGateataGlance
    5.3.2TheStaticBehaviorandRobustnessIssues
    5.3.3PerfonnanceoftheBiCMOSInverter
    5.3.4PowerConsumption
    5.3.5TechnologyScaling
    5.3.6DesigningBiCMOSDigitalGates
    5.4DigitalGalliumArsenideDesign*
    5.4.1GaAsDevicesandTheirProperties
    5.4.2GaAsDigitalCircuitDesign
    5.5Low-TemperatureDigitalCircuits*
    5.5.1Low-TemperatureSiliconDigitalCircuits
    5.5.2SuperconductingLogicCircuits
    5.6Perspective:WhentoUseHigh-PerformanceTechnologies
    5.7Summary
    5.8ToProbeFurther
    5.9ExercisesandDesignProblems
    AppendlxD:TheSchottky-BamerOiode
    Chapter6:DesigningSequentialLogicCircuits
    6.1Introduction
    6.2StaticSequentialCircuits
    6.2.1Bistability
    6.2.2Flip-FlopClassification
    6.2.3Master-SlaveandEdge-TriggeredFFs
    6.2.4CMOSStaticFlip-Flops
    6.2.5BipolarStaticFlip-Flops
    6.3DynamicSequentia)Circuits
    6.3.1ThePseudostaticLatch
    6.3.2TheDynamicTwo-PhaseFlip-Flop
    6.3.3TheC2MOSLatch
    6.3.4NORA-CMOS-ALogicStyleforPipelinedStructures
    6.3.5TrueSingle-PhaseClockedLogic(TSPCL)
    6.4Non-BistableSequentialCircuits
    6.4.1TheSchmittTrigger
    6.4.2MonostableSequentialCircuits
    6.4.3AstableCircuits
    6.5Perspective:ChoosingaClockingStrategy
    6.6Summary
    6.7ToProbeFunher
    6.8ExercisesandDesignProblems
    PART11:ASYSTEMSPERSPECTIVE
    Chapter7:DesigningArithmeticBuildingBlocks
    7.1Introduction
    7.2DatapathsinDigitalProcessorArchitectures
    7.3TheAdder
    7.3.1TheBinaryAdder:Definitions
    7.3.2TheFullAdder:CircuitDesignConsiderations
    7.3.3TheBinaryAdder:LogicDesignConsiderations
    7.4TheMultiplier
    7.4.1TheMultiplier:Definitions
    7.4.2TheArrayMultiplier
    7.4.3OtherMultiplierStructures
    7.5TheShifter
    7.5.1BarrelShifter
    7.5.2LogarithmicShifter
    7.6OtherArithmeticOperators
    7.7PowerConsiderationsinDatapathStructures
    7.7.1ReducingtheSupplyVoltage
    7.7.2ReducingtheEffectiveCapacitance
    7.8Perspective:De.signasaTrade-off
    7.9Summary
    7.10ToProbeFurther
    7.11ExercisesandDesignProblems
    AppendixE:FromDatapathSchematicstoLayout
    Chapter8:CopingwlthInterconnect
    8.1Introduction
    8.2CapacitiveParasitics
    8.2.1ModelingInterconnectCapacitance
    8.2.2CapacitanceandReliability-CrossTalk
    8.2.3CapacitanceandPerformanceinCMOS
    8.2.4CapacitanceandPerformanceinBipolarDesign
    8.3ResistiveParasitics
    8.3.1ModelingandScalingofInterconnectResistance
    8.3.2ResistanceandReliability-OhmicVoltageDrop
    8.3.3Electromigration
    8.3.4ResistanceandPerformance-RCDelay
    8.4InductiveParasitics
    8.4.1SourcesofParasiticInductances
    8.4.2InductanceandReliability-VoltageDrop
    8.4.3InductanceandPerformance-TransmissionLin5eEffects
    8.5CommentsonPackagingTechnology
    8.5.1PackageMaterials
    8.5.2InterconnectLevels
    8.5.3ThennalConsiderationsinPackaging
    8.6Perspective:WhentoConsiderInterconnectParasitics
    8.7ChapterSummary
    8.8ToProbeFurther
    8.9ExercisesandDesignProblems
    Chapter9:TimingIssuesinDigitalCircuits
    9.1Introduction
    9.2ClockSkewandSequentialCircuitPerformance
    9.2.1Single-PhaseEdge-TriggeredClocking
    9.2.2Two-PhaseMaster-SlaveClocking
    9.2.3OtherClockingStyles
    9.2.4HowtoCounterClockSkewProblems
    9.2.5CaseStudy-TheDigitalAlpha21164Microprocessor
    9.3Self-TimedCircuitDesign*
    9.3.1Selt-TimedConcept
    9.3.2Completion-SignalGeneration
    9.3.3Self-TimedSignaling
    9.4SynchronizersandArbiters*
    9.4.1Synchronizers-ConceptandImplementation
    9.4.2Arbiters
    9.5ClockGenerationandSynchronization*
    9.5.1ClockGenerators
    9.5.2SynchronizationattheSystemLevel
    9.6Perspective:SynchronousversusAsynchronousDesign
    9.7Summary
    9.8ToProbeFurther
    9.9Exerci.sesandDesignProblems
    Chapter10:DesigningMemoryandArrayStructures
    10.1Introduction
    10.2SemiconductorMemories--AnIntroduction
    10.2.1MemoryClassification
    10.2.2MemoryArchitecturesandBuildingBlocks
    10.3TheMemoryCore
    10.3.1Read-OnlyMemories
    10.3.2NonvolatileRead-WriteMemories
    10.3.3Read-WriteMemories(RAM)
    10.4MemoryPeripheralCircuitry
    10.4.1TheAddressDecoders
    10.4.2SenseAmplifiers
    10.4.3Drivers/Buffers
    10.4.4TimingandControl
    10.5MemoryReliabilityandYield
    10.5.1Signal-To-NoiseRatio
    10.5.2Memoryyield
    10.6CaseStudiesinMemoryDesign
    10.6.1TheProgrammableLogicArray(PLA)
    10.6.2A4MbitSRAM
    10.7Perspective:SemiconductorMemoryTrendsandEvolutions
    10.8Summary
    10.9ToProbeFurther
    10.10ExercisesandDesignProblems
    Chapterll:DeslgnMethodologles
    11.1Introduction
    11.2DesignAnalysisandSimulation
    11.2.1RepresentingDigitalDataasaContinuousEntity
    11.2.2RepresentingDataasaDiscreteEntity
    11.2.3UsingHigher-LevelDataModels
    11.3DesignVerification
    11.3.1ElectricalVerification
    11.3.2TimingVerification
    11.3.3Functional(orFonnal)Verification
    11.4ImplementationApproaches
    11.4.1CustomCircuitDesign
    11.4.2Cell-BasedDesignMethodology
    11.4.3Anay-BasedImplementationApproaches
    11.5DesignSynthesis
    11.5.1CircuitSynthesis
    11.5.2LogicSynthesis
    11.5.3ArchitectureSynthesis
    11.6ValidationandTestingofManufacturedCircuits
    11.6.1TestProcedure
    11.6.2DesignforTestability
    11.6.3Test-PattemGeneration
    11.7PerspectiveandSummary
    11.8ToProbeFurther
    11.9ExercisesandDesignProblems
    ProblemSolutions
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