计算机组织与结构：性能设计（第8版）（英文版）
出版时间:
2012-07
版次:
8
ISBN:
9787121170607
定价:
99.00
装帧:
平装
开本:
16开
纸张:
胶版纸
页数:
774页
字数:
1441千字
正文语种:
简体中文
-
《计算机组织与结构：性能设计（第8版）（英文版）》以Intel x86系列通用处理器和ARM系列嵌入式处理器作为主要考察实例，将当代计算机系统性能设计问题和计算机组织与结构的基本概念及原理紧密联系。首先介绍计算机的发展与演变，引入性能评价和性能设计的概念，然后以自顶而下的方式逐层展开介绍计算机系统、存储器体系结构、I/O及互连、计算机算术、指令集体系结构的设计及其实现技术、控制器设计，最后还介绍了处理器的各种并行组织技术。本书特色在于探讨和揭示面向性能的各种设计博弈和实现考量，追逐性能极大化的同时顾及系统整体的性能平衡。 WilliamStallings，作为一名顾问、讲师和17本(不包括再版)著作的作者，WilliamStallings是计算机界的一位巨擘。本书第四版获得了由美国教科书与高等院校作者协会(Text and Academic AuthoAssociation)颁发的2002年度最佳计算机与工程图书奖。他还因其大量优秀作品获得了很多其他的奖项。他从NotreDame获得电子工程硕士学位后，在MIT获得计算机科学博士学位。他维护了一个面向计算机科学的学生资源网站：http：//WilliamStallings.com/StudentSupport.html。他在PrenticeHall公司出版的所有图书均可以在网站http：//www.prenhall.com上找到。 Chapter 1 Reader’s Guide
0.1 Outline of the Book
0.2 A Roadmap for Readers and Instructors
0.3 Why Study Computer Organization and Architecture
0.4 Internet and Web Resources
PART ONE OVERVIEW
Chapter 2 Introduction
1.1 Organization and Architecture
1.2 Structure and Function
1.3 Key Terms and Review Questions
Chapter Computer Evolution and Performance
2.1 A Brief History of Computers
2.2 Designing for Performance
2.3 The Evolution of the Intel x86 Architecture
2.4 Embedded Systems and the ARM
2.5 Performance Assessment
2.6 Recommended Reading and Web Sites
2.7 Key Terms, Review Questions, and Problems
PART TWO THE COMPUTER SYSTEM
Chapter 3 A Top-Level View of Computer Function and Interconnection
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
3.5 PCI
3.6 Recommended Reading and Web Sites
3.7 Key Terms, Review Questions, and Problems
Appendix A Timing Diagrams
Chapter 4 Cache Memory
4.1 Computer Memory System Overview
4.2 Cache Memory Principles
4.3 Elements of Cache Design
4.4 Pentium Cache Organization
4.5 ARM Cache Organization
4.6 Recommended Reading
4.7 Key Terms, Review Questions, and Problems
Appendix A Performance Characteristics of Two-Level Memories
Chapter 5 Internal Memory Technology
5.1 Semiconductor Main Memory
5.2 Error Correction
5.3 Advanced DRAM Organization
5.4 Recommended Reading and Web Sites
5.5 Key Terms, Review Questions, and Problems
Chapter 6 External Memory
6.1 Magnetic Disk
6.2 RAID
6.3 Optical Memory
6.4 Magnetic Tape
6.5 Recommended Reading and Web Sites
6.6 Key Terms, Review Questions, and Problems
Chapter 7 Input/Output
7.1 External Devices
7.2 I/O Modules 2
7.3 Programmed I/O
7.4 Interrupt-Driven I/O 8
7.5 Direct Memory Access
7.6 I/O Channels and Processors
7.7 The External Interface: FireWire and Infiniband
7.8 Recommended Reading and Web Sites
7.9 Key Terms, Review Questions, and Problems
Chapter 8 Operating System Support
8.1 Operating System Overview
8.2 Scheduling
8.3 Memory Management
8.4 Pentium Memory Management
8.5 ARM Memory Management
8.6 Recommended Reading and Web Sites
8.7 Key Terms, Review Questions, and Problems
PART THREE THE CENTRAL PROCESSING UNIT
Chapter 9 Computer Arithmetic
9.1 The Arithmetic and Logic Unit (ALU)
9.2 Integer Representation
9.3 Integer Arithmetic
9.4 Floating-Point Representation
9.5 Floating-Point Arithmetic
9.6 Recommended Reading and Web Sites
9.7 Key Terms, Review Questions, and Problems
Chapter 10 Instruction Sets: Characteristics and Functions
10.1 Machine Instruction Characteristics
10.2 Types of Operands
10.3 Intel x86 and ARM Data Types
10.4 Types of Operations
10.5 Intel x86 and ARM Operation Types
10.6 Recommended Reading
10.7 Key Terms, Review Questions, and Problems
Appendix A Stacks
Appendix B Little, Big, and Bi-Endian
Chapter 11 Instruction Sets: Addressing Modes and Formats
11.1 Addressing
11.2 x86 and ARM Addressing Modes
11.3 Instruction Formats
11.4 x86 and ARM Instruction Formats
11.5 Assembly Language
11.6 Recommended Reading
11.7 Key Terms, Review Questions, and Problems
Chapter 12 Processor Structure and Function
12.1 Processor Organization
12.2 Register Organization
12.3 The Instruction Cycle
12.4 Instruction Pipelining
12.5 The x86 Processor Family
12.6 The ARM Processor
12.7 Recommended Reading
12.8 Key Terms, Review Questions, and Problems
Chapter 13 Reduced Instruction Set Computers (RISCs)
13.1 Instruction Execution Characteristics
13.2 The Use of a Large Register File
13.3 Compiler-Based Register Optimization
13.4 Reduced Instruction Set Architecture
13.5 RISC Pipelining
13.6 MIPS R4000
13.7 SPARC
13.8 The RISC versus CISC Controversy
……
-
内容简介:
《计算机组织与结构：性能设计（第8版）（英文版）》以Intel x86系列通用处理器和ARM系列嵌入式处理器作为主要考察实例，将当代计算机系统性能设计问题和计算机组织与结构的基本概念及原理紧密联系。首先介绍计算机的发展与演变，引入性能评价和性能设计的概念，然后以自顶而下的方式逐层展开介绍计算机系统、存储器体系结构、I/O及互连、计算机算术、指令集体系结构的设计及其实现技术、控制器设计，最后还介绍了处理器的各种并行组织技术。本书特色在于探讨和揭示面向性能的各种设计博弈和实现考量，追逐性能极大化的同时顾及系统整体的性能平衡。
-
作者简介:
WilliamStallings，作为一名顾问、讲师和17本(不包括再版)著作的作者，WilliamStallings是计算机界的一位巨擘。本书第四版获得了由美国教科书与高等院校作者协会(Text and Academic AuthoAssociation)颁发的2002年度最佳计算机与工程图书奖。他还因其大量优秀作品获得了很多其他的奖项。他从NotreDame获得电子工程硕士学位后，在MIT获得计算机科学博士学位。他维护了一个面向计算机科学的学生资源网站：http：//WilliamStallings.com/StudentSupport.html。他在PrenticeHall公司出版的所有图书均可以在网站http：//www.prenhall.com上找到。
-
目录:
Chapter 1 Reader’s Guide
0.1 Outline of the Book
0.2 A Roadmap for Readers and Instructors
0.3 Why Study Computer Organization and Architecture
0.4 Internet and Web Resources
PART ONE OVERVIEW
Chapter 2 Introduction
1.1 Organization and Architecture
1.2 Structure and Function
1.3 Key Terms and Review Questions
Chapter Computer Evolution and Performance
2.1 A Brief History of Computers
2.2 Designing for Performance
2.3 The Evolution of the Intel x86 Architecture
2.4 Embedded Systems and the ARM
2.5 Performance Assessment
2.6 Recommended Reading and Web Sites
2.7 Key Terms, Review Questions, and Problems
PART TWO THE COMPUTER SYSTEM
Chapter 3 A Top-Level View of Computer Function and Interconnection
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
3.5 PCI
3.6 Recommended Reading and Web Sites
3.7 Key Terms, Review Questions, and Problems
Appendix A Timing Diagrams
Chapter 4 Cache Memory
4.1 Computer Memory System Overview
4.2 Cache Memory Principles
4.3 Elements of Cache Design
4.4 Pentium Cache Organization
4.5 ARM Cache Organization
4.6 Recommended Reading
4.7 Key Terms, Review Questions, and Problems
Appendix A Performance Characteristics of Two-Level Memories
Chapter 5 Internal Memory Technology
5.1 Semiconductor Main Memory
5.2 Error Correction
5.3 Advanced DRAM Organization
5.4 Recommended Reading and Web Sites
5.5 Key Terms, Review Questions, and Problems
Chapter 6 External Memory
6.1 Magnetic Disk
6.2 RAID
6.3 Optical Memory
6.4 Magnetic Tape
6.5 Recommended Reading and Web Sites
6.6 Key Terms, Review Questions, and Problems
Chapter 7 Input/Output
7.1 External Devices
7.2 I/O Modules 2
7.3 Programmed I/O
7.4 Interrupt-Driven I/O 8
7.5 Direct Memory Access
7.6 I/O Channels and Processors
7.7 The External Interface: FireWire and Infiniband
7.8 Recommended Reading and Web Sites
7.9 Key Terms, Review Questions, and Problems
Chapter 8 Operating System Support
8.1 Operating System Overview
8.2 Scheduling
8.3 Memory Management
8.4 Pentium Memory Management
8.5 ARM Memory Management
8.6 Recommended Reading and Web Sites
8.7 Key Terms, Review Questions, and Problems
PART THREE THE CENTRAL PROCESSING UNIT
Chapter 9 Computer Arithmetic
9.1 The Arithmetic and Logic Unit (ALU)
9.2 Integer Representation
9.3 Integer Arithmetic
9.4 Floating-Point Representation
9.5 Floating-Point Arithmetic
9.6 Recommended Reading and Web Sites
9.7 Key Terms, Review Questions, and Problems
Chapter 10 Instruction Sets: Characteristics and Functions
10.1 Machine Instruction Characteristics
10.2 Types of Operands
10.3 Intel x86 and ARM Data Types
10.4 Types of Operations
10.5 Intel x86 and ARM Operation Types
10.6 Recommended Reading
10.7 Key Terms, Review Questions, and Problems
Appendix A Stacks
Appendix B Little, Big, and Bi-Endian
Chapter 11 Instruction Sets: Addressing Modes and Formats
11.1 Addressing
11.2 x86 and ARM Addressing Modes
11.3 Instruction Formats
11.4 x86 and ARM Instruction Formats
11.5 Assembly Language
11.6 Recommended Reading
11.7 Key Terms, Review Questions, and Problems
Chapter 12 Processor Structure and Function
12.1 Processor Organization
12.2 Register Organization
12.3 The Instruction Cycle
12.4 Instruction Pipelining
12.5 The x86 Processor Family
12.6 The ARM Processor
12.7 Recommended Reading
12.8 Key Terms, Review Questions, and Problems
Chapter 13 Reduced Instruction Set Computers (RISCs)
13.1 Instruction Execution Characteristics
13.2 The Use of a Large Register File
13.3 Compiler-Based Register Optimization
13.4 Reduced Instruction Set Architecture
13.5 RISC Pipelining
13.6 MIPS R4000
13.7 SPARC
13.8 The RISC versus CISC Controversy
……
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