未读消息消息

店铺

我的订单收藏

拍卖

拍卖交易我的竞拍收藏

我的好友资金账户

客服 |

帮助中心 9:00-20:30 在线留言

客服电话

010-89648155

服务时间

客服咨询 8:00-21:00

纠纷处理 9:00-21:00

图书审核 9:00-18:00

监督与建议

请选择

手机孔网

Design Through Verilog HDL

Design Through Verilog HDL

分享

作者: T. R. Padmanabhan 著 , B. Bala Tripura Sundari 著

出版社: Wiley-IEEE Press

出版时间: 2003-11

版次: 1

ISBN: 9780471441489

定价: 1499.90

装帧: 精装

页数: 472页

正文语种: 英语

分类: 外文古旧书>英文书>计算机与互联网

A comprehensive resource on Verilog HDL for beginners and experts Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool. Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant. Other important topics covered include: Primitives Gate and Net delays Buffers CMOS switches State machine design Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design. Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource. T. R. PADMANABHAN, PhD, is Dean-Engineering, Amrita Institute of Technology, Amrita Vishwa Vidyapeetham, (Amrita University), Ettimadai (PO), Coimbatore, India. He is a Senior Member of IEEE as well as a Fellow of both India’s IE and IETE.B. BALA TRIPURA SUNDARI is a Senior Lecturer in the ECE Department of the Amrita Institute of Technology. She is a senior faculty member in the microelectronics center at the institute. She is a member of India’s IETE and ISTE.
内容简介:
A comprehensive resource on Verilog HDL for beginners and experts Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool. Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant. Other important topics covered include: Primitives Gate and Net delays Buffers CMOS switches State machine design Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design. Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.
作者简介:
T. R. PADMANABHAN, PhD, is Dean-Engineering, Amrita Institute of Technology, Amrita Vishwa Vidyapeetham, (Amrita University), Ettimadai (PO), Coimbatore, India. He is a Senior Member of IEEE as well as a Fellow of both India’s IE and IETE.B. BALA TRIPURA SUNDARI is a Senior Lecturer in the ECE Department of the Amrita Institute of Technology. She is a senior faculty member in the microelectronics center at the institute. She is a member of India’s IETE and ISTE.

查看详情

相关分类

Literature&Fiction文学与虚构 ScienceFiction&Fantasy科幻与玄幻 Romance浪漫小说 Mystery&Thrillers神秘与惊悚 Teens青少年读物 Biographies&Memoirs传记与自传 Comics&GraphicNovels动漫与绘画小说 ELT英语学习 Reference参考书 StandardTest标准考试 Business&Investing商业与投资 Self-Help励志自助

Design Through Verilog HDL

九品

香书斋

上海市虹口区

平均发货16小时成功完成率96.49%

￥288.00

券

100减20

立即购买加入购物车